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Deccan Herald - Synopsys unveils new chip design system
archive.deccanherald.com
Briefing reporters, Synopsys Senior Director Global Technical Services, Jai Durgam, said, “The new design system incorporates four core ...
Andes 32-bit CPU IP Cores Implemented on GLOBALFOUNDRIES ...
www.design-reuse-china.com
We are also excited about Andes newest RISC-V CPU IP. Customer demand is pushing this Open Architecture solution and GF is pleased to support Andes' customer solutions for the IoT and RF Connectivity markets," said Jai Durgam, Vice President, Customer Design Enablement of GLOBALFOUNDRIES. About Andes
Cadence Announces Digital and Signoff Flow Support for Body-Bias...
www.cadence.com
Cadence announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for the GLOBALFOUNDRIES...
Cadence Announces Digital and Signoff Flow Support for ...
www.cadence.com
“Our collaboration with Cadence helps validate its digital and signoff flows that support FDX body-bias interpolation, which is a key differentiator with our FD-SOI process technologies” said Jai Durgam, vice president, Customer Design Enablement at GF.
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