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トラックドライバー甲子園アワード第１回全国大会

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トラックドライバー甲子園アワードが遂に開催運送業界から日本を元気にしたいという想いを持つ全国の同志により開催される運業界で働くトラックドライバーが最高に輝ける場を提供する大会です全国からエントリーされた運業業界のうち独自の選考基準で選...

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US A - Semiconductor device having CMOS circuit and bipolar...

patents.google.com

In a semiconductor device where a CMOS circuit and a bipolar circuit are mixed, the bipolar circuit is operated between a first power supply voltage and...

EP A1 - Silicon on insulator master slice semiconductor...

patents.google.com

A master slice semiconductor IC has a SOI substrate and a plurality of basic cells arranged in a matrix on the SOI substrate. The basic cell includes a...

US B2 - Clutch weight for wet centrifugal clutch and process...

patents.google.com

In a clutch weight for a wet centrifugal clutch, a weight member is formed of a sintered metal. Thus, the cost can be reduced, while stabilizing the...

US B2 - Clutch outer Google Patents

patents.google.com

A clutch outer includes a cylindrical portion with a plurality of slits defined therein which extend in an axial direction of the cylindrical portion....

US A - Semiconductor memory device with several access enabled...

patents.google.com

In a semiconductor memory device, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells is connected to one of a...

US A1 - Latch circuit and semiconductor integrated circuit...

patents.google.com

A semiconductor integrated circuit so configured to stop the supplying of an electric power to a logic circuit in a standby mode, thereby to realize a...

US A - Bipolar-cmos integrated circuit having a structure...

patents.google.com

Herein disclosed is a bipolar-CMOS semiconductor circuit having a semiconductor substrate, an N - epitaxial layer formed on the semiconductor substrate,...

US B2 - Designing method of semiconductor integrated circuit...

patents.google.com

A designing method of a semiconductor integrated circuit is composed of providing a library storing a macro mask pattern for a macro circuit including...

US B1 - Multivalued mask read-only memory Google...

patents.google.com

A multivalued mask ROM is configured by arranging cell transistors in a matrix form, which is defined by wiring word lines and ground lines in rows and...

US B1 - Master-slice type semiconductor IC device with...

patents.google.com

Disclosed is a method for making a semiconductor integrated circuit device used to form a p-channel MOS field-effect transistor and a n-channel MOS...

US B1 - Latch type sense amplifier circuit Google...

patents.google.com

A latch type sense amplifier circuit comprises first and second latch circuits which output the same output signals when a potential difference between a...

US A - Gate array integrated semiconductor device having...

patents.google.com

In an unused unit cell of a gate array integrated semiconductor device, a P-type semiconductor region is connected to a ground potential connection and...

US B1 - Dual gate semiconductor device for shortening channel...

patents.google.com

In a semiconductor device including a MOSFET, a first semiconductor layer is formed over a silicon substrate and has a gate region. Further, a second...

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Kouichi Kumagai Free People Check

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トラックドライバー甲子園アワード第１回全国大会

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Miscellaneous

US A - Semiconductor device having CMOS circuit and bipolar...

EP A1 - Silicon on insulator master slice semiconductor...

US B2 - Clutch weight for wet centrifugal clutch and process...

US B2 - Clutch outer Google Patents

US A - Semiconductor memory device with several access enabled...

US A1 - Latch circuit and semiconductor integrated circuit...

US A - Bipolar-cmos integrated circuit having a structure...

US B2 - Designing method of semiconductor integrated circuit...

US B1 - Multivalued mask read-only memory Google...

US B1 - Master-slice type semiconductor IC device with...

US B1 - Latch type sense amplifier circuit Google...

US A - Gate array integrated semiconductor device having...

US B1 - Dual gate semiconductor device for shortening channel...